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Revision 1.4
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AS5132
Datasheet - Detailed Description
Figure 11. OTP Programming Connection
Note:   The maximum capacitive load at PROG in normal operation should be less than 20pF. However, during programming the capacitors 
C1+C2 are needed to buffer the programming voltage during current spikes, but they must be removed for normal operation. To
overcome this contradiction, the recommendation is to add a diode (4148 or similar) between PROG and VDD as shown in Figure 11
(special case setup), if the capacitors can not be removed at final assembly.
Due to D1, the capacitors C1+C2 are loaded with VDD-0.7V at startup, hence not influencing the readout of the internal OTP registers.
During programming the OTP, the diode ensures that no current is flowing from PROG (8V to 8.5V) to VDD (5V).
In the standard case (see Figure 11), the verification of a correct OTP readout must be done by analog readback. The special case
setup provides the analog readback of the OTP as well.
As long as the PROG pin is accessible it is recommended to use standard setup. In case the PROG pin is not accessible at final
assembly, the special setup is recommended.
7.1.3   Programming Verification
After programming, the programmed OTP bits must be verified using the following methods:
Digital Read Out (Mandatory): After sending a READ OTP command, the readback information must be the same as programmed 
information. Otherwise, it indicates that the programming was not performed correctly.
Note:   Either Digital Verification or Analog Verification must be carried out in addition to the Digital Read Out.
Digital Verification: Checking the EZ ERR bit (0 = OK, 1 = error)
i) At room temperature
ii) Right after the programming
Analog Verification: By switching into Extended Mode and sending a READ ANA command, the pin PROG becomes an output sending an 
analog voltage with each clock representing a sequence of the bits in the OTP register (starting with D61). A voltage of <500mV indicates a
correctly programmed bit (1) while a voltage level between 2V and 3.5V indicates a correctly unprogrammed bit (0). Any voltage level in
between indicates incorrect programming.
VDD
V
SUPPLY
PROG
GND
C1
C2
100nF
10礔
V
zapp
V
prog
PROM Cell
Maximum
parasitic cable
inductance
L<50nH
Standard Case
VDD
V
SUPPLY
PROG
GND
C1
C2
100nF
10礔
V
zapp
V
prog
PROM Cell
L<50nH
Special Case
Remove for normal operation
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